Testing can occur in three different phases of a system on a chip (SoC) life-cycle: a manufacturing test (MFGT), a power-on-self-test (POST), and a mission mode self-test (MMST). Each phase of the testing process carries its own requirements and goals.
In the first phase of testing, MFGT, the fabricated memories are tested with memory built-in-self-test (MBIST), in which the MBIST runs a series of data patterns, writes the data patterns into the memory array, and then reads the outputs from the memory array for comparison to expected data. Further, logic around the memories is tested using a scan test (e.g., automatic test pattern generation (ATPG)), functional patterns, or logic built-in-self-test (LBIST). The primary goal of MFGT is to assure that the highest level quality of silicon (QoS) is achieved. This can be achieved by, for example, stressing the SoC. However, even with the above testing strategies, certain failures can still escape test. For example, because (i) MBIST only tests between the MBIST engine and the MBIST comparator and (ii) ATPG is only tested up to (and from) the functional flops near the memory, the logic that feeds the memory arrays (or proceeds from them) that lies between the two testing strategies can be difficult to test. Error correction code (ECC) logic, is an example of such logic. ECC logic, which will be described in greater detail below, is the means for tolerating intermittent faults during the SoC's functional operation.
Conventional solutions to resolve the above testing exposure problem include: (i) ATPG RAM sequential (e.g., to push patterns through memories on functional paths), (ii) memories with embedded scan segments (e.g., scan chains) to test the functional paths, and (iii) have MBIST connect and control functional paths directly. However, ATPG RAM sequential can only be used in the MFGT phase but not the POST and MMST phases. Further, embedding scan segments to test the functional path increases the memory area. In addition, even though a test can be applied to the functional paths to and from the memory IP, internally, to the memory, that path is to scan flops and not truly the full functional path with its functional operation timing. Lastly, connecting MBIST to the functional paths to control them directly will likely impact function timing with additional multiplexing. Further, controlling the functional paths directly with MBIST is only beneficial if it is applied to the physical memory module. However, it is not as effective with logical memory modules, e.g., those including ECC logic.
The second phase of testing, POST, varies dependent on the technology node and market that the SoC is targeting. As its name implies, POST occurs when the SoC is activated prior to normal operations commencing, e.g., starting of a car. POST usually includes MBIST for testing the physical memory module and LBIST for testing the combinational logic within logical memory modules (ATPG testing can only be utilized for MFGT). Further, the test time limitation is more prominent in POST than MFGT. However, the test quality level for POST is not as stringent as MFGT because it is assumed that the SoC had been thoroughly tested at MFGT. As such, POST is more of a sign-off test from a functional point-of-view. Specifically, POST ensures that the SoC will operate as expected during functional operation until the next POST (e.g., the next time the car is started). However, POST also encounters some of the same problems that exist with MFGT, i.e., the inability to functionally test the ECC logic in the design. ECC logic is used for tolerating intermittent faults in the memories during the functional operation of the SoC. As such, if an error occurs in the ECC logic that masks a real failure, a system utilizing the SoC would be left unaware of the failure until it is too late. For safety-critical applications (e.g., automotive, pacemakers, etc.), such failures could prove deadly if not diagnosed early enough. Accordingly, the possibility of masked errors needs to be determined at least by POST so that the system is given enough time to respond prior to normal operations commencing.
In the third phase of testing, MMST, there are generally two approaches. In the first approach, partitions within the SoC design are scheduled to be taken off-line. Once offline, some level of testing (i.e., MBIST and/or LBIST) occurs on the partitions. However, if the test being applied to the data within the partition is destructive, additional overhead (i.e., memory area and time) will be required in order to save and restore the partition data as the partition comes off and on line. Further, because time is very critical during this phase, such overhead needs to be avoided as much as possible. In the second approach, dynamic-type testing, e.g., ECC, is employed. Unlike the first approach, the ECC testing is non-destructive to the SoC's data. Further, in terms of testing memory non-destructively, ECC is the primary means of testing during the MMST phase. As such, in order to assure a quality test during MMST, the ECC logic and the interfaces to and from the memories need to be tested. As mentioned previously above, standard test strategies like MBIST, ATPG, and LBIST can leave holes in the testing of logic around the memories. Therefore, if the ECC logic is not thoroughly tested during at least one of MFGT and POST, any errors that the ECC logic may contain could prevent proper error reporting during MMST.
Accordingly, there is a need to effectively test ECC logic and the interfaces to and from the memories during at least one of MFGT and POST.